Test set for a navigational satellite receiver

ABSTRACT

A test set including a digital card tester section and a satellite  simula section is used to detect the reduced capabilities of an associated navigational satellite receiver and to isolate malfunctions therein. The digital card tester section is configured to generate digital signals (signatures) which are used to test and isolate faults in four digital system boards (cards) of the associated navigational satellite receiver. The satellite simulator section is configured to generate a facsimile of a navigational reference signal which is normally transmitted by an associated satellite system and received by the aforementioned associated navigational satellite receiver. The facsimile signal is used to test the receiver-processor section of the associated navigational satellite receiver.

CROSS-REFERENCE TO RELATED APPLICATION

The present application contains subject matter which is related to thesubject matter disclosed in U.S. patent application Ser. No. 620,659, toR. E. Bateman, entitled, "A Test Set For A Navigational SatelliteReceiver", filed June 14, 1984, and assigned to the same assignee as thepresent application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a test set for determiningthe operational status of an associated navigational satellite receiver,but more specifically, the present invention relates to a test sethaving the dual capability of isolating faults in a digital section ofthe associated navigational satellite receiver and generating afacsimile of a navigational satellite reference signal for isolatingfaults in a receiver-processor section of the aforementioned associatednavigational satellite receiver.

2. Description of the Prior Art

The AN/SRN-19(V)2 is an automatic shipboard radio navigational set thatprovides a continuous display of the position of the ship upon which itis associated. The ship's position, which is normally obtained by deadreckoning on the ship's true speed and heading, is periodically updatedby fixes on a plurality of satellites. These satellites are part of theNavy Navigational Satellite System (NNSS), which is a world wide, allweather navigational system consisting of, inter alia, five satellitesin polar orbits. The AN/SRN-19(V)2 shipboard radio navigational set,aforementioned, operates on a dedicated navigational program oralgorithm which enables navigators to obtain accurate fixes using thedata received from one of the five orbiting satellites.

Each satellite orbits the earth in approximately 107 minutes andcontinually transmits the following phase modulated data every twominutes on two radio frequency (RF) carriers: (1) time synchronizationsignals, (2) a 400 MHz signal, and (3) fixed and variable parametersdescribing the satellite's orbit. It should be mentioned that theforegoing satellite system is also used by commercial concerns.

The AN/SRN-19(V)2 radio navigational set comprises, inter alia, anantenna, an RF amplifier and a receiver-processor including a receiverportion and a data processor portion. The receiver portion extracts,amplifies and formats message information from the RF signal transmittedby the satellite and measures the doppler shift of this same signal. Thereconstructed doppler shift of the satellite signal results from arelative motion between the receiver and the satellite. The message dataobtained by the phase modulation of the RF carrier describes thesatellite's position at an even two minute universal time period. Thedata processor processes inputs from the receiver, the ship'selectromagnetic log and gyrocompass through two synchro-to-digital (S/D)converters and a receiver-processor keyboard. The data processor thenperforms computations and provides the desired outputs to a front paneldisplay, a readout indicator, a printer and a cassette recorder.

It has been determined over a period of years that users of the NNSSwere having problems determining whether the receiving equipment, forexample, the AN/SRN-19(V)2, for obtaining their position was operatingcorrectly, whether the receiving equipment was within the calibrationrange required for certification thereof, and, indeed, at times at sea(where references as to the ship's position were not available), whetherthe receiving equipment was operational.

Consequently, there is a need in the prior art for the capability ofcertifying satellite navigational receivers for operational readiness,and to facilitate and enable the end users to determine if there is, infact, a failure and what the failed part is. Thus, the logistics couldthen be set-up so that instead of returning the particular navigationalsatellite receiver to a base depot for repair, the cognizant operatorwould be able to determine, in the field, what are the failed parts andrequest the particular replacement therefor.

The test set, according to the present invention, is configured tooperate with the AN/SRN-19(V)2 radio navigational set, which is fullydisclosed in the publication entitled, "Shipboard Operations andMaintenance Manual" (NAVELEX 0967-LP-634-9010).

OBJECTS OF THE INVENTION

Accordingly, an important object of the present invention is toconfigure a test set for operation with a predetermined associatednavigational satellite receiver so as to certify the readiness thereof.

Another object of the present invention is to configure the test set soas to not only test the pertinent sections of the associatednavigational satellite receiver, but, also, to be able to localize afailed part therein.

Yet another object of the present invention is to configure the test setto be portable and easy to interface with the predetermined associatednavigational satellite receiver.

A further object of the present invention is to configure the test setso that it maintains its calibration over a long period of time and iseasy to operate under field conditions.

Still a further object of the present invention is to configure the testset so as to generate a facsimile of the actual satellite signals so asto activate the "normal functions" of the predetermined associatednavigational satellite receiver, so that the test set can be used as atraining device (simulator) aboard ship when the ship is out of "view"of the Navy Navigational Satellite System (NNSS).

SUMMARY OF THE INVENTION

The test set, according to the present invention, by which the foregoingand other objects, features and advantages are accomplished ischaracterized, inter alia, by configuring it to comprise two independenttest sections, which are a digital card tester section and a satellitesimulator section.

The digital card tester section is used to test and isolate faults infour digital boards (cards) of an associated navigational satellitereceiver, for example, the AN/SRN-19(V)2. A microprocessor portion ofthe digital card tester section is configured to generate a fixedpattern of test signals (signatures) with a predetermined responsepattern. A fail indicator illuminates when any response deviationoccurs. A pass indicator illuminates when a particular circuit board hassuccessfully completed the test.

The satellite simulator section generates a satellite type radiofrequency (RF) signal at a predetermined frequency for testing thereceiver section of the aforementioned associated navigational satellitereceiver, by signal insertion or radiation, in the absence of a systemsatellite. Various signal levels, degrees of phase modulation and signalfrequencies are selectable by controls and switches associated with thesatellite simulator section.

The aforementioned lights, controls and switches, inter alia, aredisposed on and affixed to an escutcheon panel and a chassiscombination, along with a common power supply. This configurationunifies the digital card test section and the satellite simulatorsection into a complete and portable test set.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects and novel features and advantages of thepresent invention will be more apparent from the following moreparticular description of the preferred embodiments as illustrated inthe accompaning drawings, in which:

FIG. 1 is a block diagram representation of the digital card testersection of a test set for a navigational satellite receiver including,inter alia, a microprocessor portion and a read-only memory (ROM)portion, according to the present invention;

FIG. 2 is a specific pictorial flowchart illustrating the program storedin the ROM portion of FIG. 1 and the steps necessary for the properoperation of the microprocessor portion of FIG. 1 during the testing ofone of the four digital system boards (cards) of the associatednavigational satellite receiver;

FIG. 3 is a block diagram representation of the satellite simulatorsection of the test set for a navigational satellite receiver, accordingto the present invention depicting, inter alia, a radio frequencyportion and a digital portion thereof; and

FIG. 4 is a waveform diagram illustrating the interrelationship of theradio frequency portion and the digital portion of the satellitesimulator section of FIG. 3 during the operation thereof.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following is a description of the digital card tester section of atest set for a navigational satellite receiver, according to the presentinvention. A description of the satellite simulator section followshereinafter.

Referring then to FIG. 1, the digital card tester (DCT) section 10comprises a microprocessor 12, a system clock 14, a read-only memory(ROM) 16 and a random access memory (RAM) 18. The DCT section 10 furthercomprises a digital card select device 20, a system reset switch 22, abi-directional buffer 24, a digital card socket device 26 including aplurality of digital sockets 28-1, 28-2, 28-3 and 28-4, a lamp driver 30having a corresponding pass indicator LED 1, a lamp driver 32 having acorresponding fail indicator LED 2 and a display device 34. For purposesof the present invention LED 1 and 2 are green and red light-emittingdiodes, respectively.

Still referring to FIG. 1, the system clock 14 generates periodicsignals used for synchronization and is operatively connected to themicroprocessor 12. The ROM 16 and the RAM 18 are also operativelyconnected to the microprocessor 12. The microprocessor 12 is configuredto execute the program stored in the ROM 16 and execute and interpretother instructions from the system reset switch 22 and the digital cardselect device 20. The microprocessor 12, via its bus control line (BCL)and its input/output control line (I/OCL), in cooperation with thebi-directional buffer 24, controls the flow of information to/from theRAM 18. The lamp driver 30 drives the pass indicator LED 1, and the lampdriver 30 drives the fail indicator LED 2, both being under the controlof the microprocessor 12. In addition, the microprocessor 12 isoperatively connected to the display device 34 for displaying theresults of the test of a particular digital circuit board connected to aparticular one of the digital sockets 28-1, 28-2, 28-3 or 28-4 of thedigital card socket device 26. The operation of the DCT section 10 ofFIG. 1 will be further described and explained hereinafter under theheading "Statement of the Operation."

FIG. 2, is a specific pictorial flowchart illustrating the program andsteps necessary for the proper operation of the digital card testersection of FIG. 1 and will be used in the discussion of the operationthereof. The process blocks and the decision blocks in theaforementioned flowchart are designated with the numerals 36 through 78.

Following now is a brief description of the satellite simulator sectionof the test set for a navigational satellite receiver, according to thepresent invention.

Referring then now to FIG. 3, the satellite simulator section 80comprises a radio frequency portion 82, a digital portion 84 and aninterface portion 86. The radio frequency portion 82 is configured togenerate a crystal referenced approximately 400 MHz signal, which is ±60degrees phase modulated. The digital portion 84 is configured togenerate a sequence of digital data for driving the radio frequencyportion 82. The interface portion 86 is configured to interface betweenthe aforementioned radio frequency portion 82 and the associatednavigational satellite receiver under test.

To continue, the radio frequency portion 82 comprises acrystal-controlled oscillator device 88 operatively connected to abuffer/mode select device 90 which is configured to automatically switchbetween the output of the aforementioned crystal-controlled oscillatordevice 88 and an external input signal from the associated navigationalsatellite receiver under test via an escutcheon panel (not shown). Aphase coaparator/loop filter 92 is part of a phase-locked-loop (PLL)comprising a frequency divider 94 and a voltage controlled oscillator(VCO) 96. The output of the buffer/mode select device 90 drives thephase comparator/loop filter 92, which, in turn, drives theaforementioned VCO 96 whose output feeds the frequency divider 94. Inturn, the frequency divider 94 feeds the aforementioned phasecomparator/loop filter 92 thereby completing the phase-locked-loopfeedback path. The frequency divider 94 also drives a frequency divider98 whose output is operatively connected to the digital portion 84 ofthe satellite simulator section 80.

Still referring to FIG. 3, the radio frequency portion 82 furthercomprises a frequency multiplier 100 whose input is connected to theoutput of the VCO 96. The output of the frequency multiplier 100 isoperatively connected to the input of a phase modulator device 102,which includes a phase modulator 104a, a phase modulator 104b and aphase modulator 104c each having phase delays of 0, 120 and 60 degrees,respectively. The phase modulator device 102 is also operativelyconnected to the digital portion 84. The output of the phase modulatordevice 102 is operatively connected to the interface portion 86 of thesatellite simulator section 80.

The digital portion 84 of the satellite simulator section 80 comprises atest message generator 106, a sync word generator 108, an output controldevice 110 and a count down divider 112. The test message generator 106and the sync word generator 108 are, both, operatively connected to theoutput control device 110 whose output signals a, b, and c drive thecorresponding phase modulators 104a, 104b and 104c of the phasemodulator 102. The input of the test message generator 106 and the inputof the count down divider 112 are, both, driven by the frequency divider98 of the radio frequency portion 82. The test message generator 106 andthe sync word generator 108 are activated by switches (not shown) on theaforementioned escutcheon panel. Along with a common chassis and powersupply (not shown), the aforementioned digital card tester section 10 ofFIG. 1 and the satellite simulator section 80 of FIG. 2 are unified intoa complete and portable test set.

To continue, the interface portion 86 comprises a direct/indirect testcontrol device 114, an offset mixer 116, a radio frequency (RF) switch118 and a tri-level attenuator 120. The input of the offset mixer 112 isdriven by the output of the aforementioned phase modulator device 102.The output of the count down divider 112 of the digital portion 84 alsois operatively connected to the offset mixer 116. The output of themixer drives the RF switch 118 which directs the signal at its inputeither to the tri-level attenuator 120 or to the aforementionedescutcheon panel as directed by the direct/indirect test control device114. The direct/indirect test control device 114 also is operativelyconnected to the tri-level attenuator 120. In addition, switches (notshown) on the aforementioned escutcheon panel operate to control thepower level output of the tri-level attenuator 120.

More about the coaction and operation of the foregoing elements of theradio frequency portion 82, the digital portion 84 and the interfaceportion 86 of the satellite simulator section 80 will be explainedhereinafter under the heading "Statement of the Operation."

STATEMENT OF THE OPERATION

Details of the operation, according to the digital card tester sectionof the present invention, are explained in conjunction with FIGS. 1 and2. Details of the operation, according to the satellite simulatorsection of the present invention, are explained in conjunction withFIGS. 3 and 4.

Referring first to FIGS. 1 and 2 as viewed concurrently, the digitalcard select device 20 is set to a digital socket position correspondingto a digital card "i" of a plurality of digital cards "K" to be tested,and generates a predetermined digital word in response to the selection.The digital card "i" is inserted in the proper one of the digitalsockets 28-1 through 28-4 of the digital card socket device 26, eachdigital socket being configured one-to-one for each digital systemboard. Then, the system reset switch 22 is depressed, as indicated bythe decision block 36, thereby causing an interrupt to themicroprocessor 12. The microprocessor 12 is initialized (as indicated byprocess blocks 38, 40 and 42, decision block 44 and process block 46) byscanning the digital card select device 20, as depicted by process block48, to direct it to the proper memory location in the ROM 16. Thismemory location is read into the microprocessor 12 and then stored inthe RAM 18, as indicated by the process block 52 with the validation ofthe correct switch settings of block 48 being accomplished as indicatedby block 50. The foregoing data consist of a self-test and the programin the ROM 16 used to test the plurality of digital cards "K" from theassociated navigational satellite receiver, which for purposes of thepresent invention is the AN/SRN-19(V)2. This data contain a test programhaving a test pattern and a signature response designed for theplurality of digital cards "K" under test.

To continue, simultaneously with reading the digital card select device20, the microprocessor 12 turns off the pass indicator LED 1 via thelamp driver 30, and the fail indicator LED 2 via the lamp driver 32.Concurrently, the microprocessor 12 performs the self-test, as indicatedby the process blocks 38, 40 and 42, and the decision block 44 and theprocess block 46. At the completion of the self-test, both the passindicator LED 1 and the fail indicator LED 2 are turned on and off toverify proper operation. This aspect of the program is illustrated bythe process block 46, aforementioned.

Still referring to FIGS. 1 and 2 as viewed concurrently, themicroprocessor 12 now directs the bi-directional buffer 24 into anoutput mode of operation, which causes the RAM 18 to transmit the testpattern data to the selected digital card "i" via the digital cardsocket device 26. The testing of the digital card "i" is then performedwith the microprocessor 12 controlling the bi-directional buffer 22. Ifduring a comparison of the signature response in the RAM 18 and theoutput from the digital card "i" a discrepancy occurs, then an errorflag is set in the microprocessor 12 (RAM 18) causing the fail indicatorLED 2 to illuminate. The foregoing operation is illusrated by theprocess block 56 which shows setting the test pattern of the digitalcards, the process block 58 which performs the test, the decision block60 which determines whether an error is present or not, the processblock 62 which increments the RAM 18 to indicate an error, the decisionblock 64 which tests the error flag in RAM 18, the process block 66which decrements the error counter, the process block 68 which if thereare no errors, stores the result in RAM 18, the process block 70 whichsets the correct error flag, the decision block 72 which counts thenumber of errors, the decision block 74 which checks the error flag inRAM 18 to see if set or if it is not set and equals zero, then throughprocess block 76 turns the pass indicator LED 1 "ON", if not set, and ifthere is an error flag set to "1" in RAM 18, then through process block78, turns the fail indicator LED 2 "ON". On the other hand, if an errorflag is not set during the test, then the pass indicator LED 1 isilluminated, as indicated by the process block 76. In addition, thestored information in ROM 18, as indicated by the process block 52, isdisplayed on the display device 34, as indicated by the process block54. Also, displayed information as to the turning on of the passindicator LED 1, or the fail indicator LED 2 is also displayed on thedisplay device 34, as indicated by the process block 54. The displayedinformation is a digital word which gives information as to what part ofthe particular digital card "i" under test failed. In this way, anoperator, if desired, can cross-reference to a print out and determinethe actual failed component.

The test pattern and signature response are temporarily stored in theRAM 18 during the testing of the digital card "i". This information isreplaced every time the digital card select device 20 and the systemreset switch 22 are depressed. The signature response comparison isperformed in the RAM 18 under the control of the microprocessor 12. Itshould be mentioned, that each of the plurality of digital cards "K" hasa unique signature response which is permanently stored in the ROM 16.Accordingly, when the test for a particular digital card "i" is selectedby the digital card select device 20, this information is transferred tothe ROM 18 for comparison and detection of errors during the test. Thesystem clock 14, as aforementioned, is a frequency control for themicroprocessor 12, the ROM 16 and the RAM 18, and, thus, determines thetest time for the testing of the plurality of digital boards "K".

The digital card tester section 10 is configured to test the fourdigital boards (cards) of the AN/SRN-19(V)2 radio navigational set.However, the techniques disclosed herein could be applied to the testingof any digital board having a known signature response that adequatelyspecifies the proper operation thereof. For the foregoing purpose, theROM 16 can be a programmable read-only memory (PROM).

The operation of the satellite simulator section 80 of the test set fora navigational satellite receiver can best be understood by referring toFIGS. 3 and 4 as viewed concurrently. The satellite simulator section 80has a mode A and a mode B operation. The mode of operation is dependenton whether the signal driving the buffer/mode select device 90 isinternally derived from the crystal-controlled oscillator 88 (mode A) orexternally derived from the associated navigational satellite receiverunder test (mode B).

Continuing, at power turn on, and when no external signal is present atthe buffer/mode select device 90, the crystal controlled oscillator 88generates a 5 MHz-325 Hz signal. This sine wave signal is amplified andsquared to a transistor-transistor logic (TTL) level in the buffer/modeselect device 90. This squared signal, at the TTL level, acts as areference input to the phase comparator/loop filter 92 whose other inputis a 5 MHz signal derived from the coaction of the frequency divider 94(divide by 20) and the voltage controlled oscillator (VCO) 96 (operatingat near 100 MHz). The phase comparator/loop filter 92 is configured tophase compare the signal from the frequency divider 94 to theconditioned signal from the buffer/mode select device 90 and filter andamplify the resulting signal. This resulting or error signal is thenapplied to the input of the VCO 96. The foregoing elements of the radiofrequency portion 82 comprise a phase-locked-loop (PLL) which operatesto maintain the frequency of the VCO 96 phase coherent to the outputsignal of the crystal-controlled oscillator 88.

Still referring to FIGS. 3 and 4 as viewed concurrently, the outputfrequency of the VCO 96 is 20 times that of the crystal-controlledoscillator device 88, i.e, 100 MHz-6.5 KHz. This signal is multiplied inthe frequency multiplier 100 (multiplied by 4) to a frequency of 400MHz-26 KHz. The output of the frequency multiplier 100 drives the phasemodulators 104a, 104b and 104c of the phase modulator device 102. Thus,the phase modulator device 102 has three signal paths between its inputand output. These signal paths are all identical except for theirelectrical lengths, i.e, phase delays. The approximately 400 MHz inputsignal to the phase modulator device 102 is directed through one or theother of the phase modulators 104a, 104b or 104c, as controlled by thecorresponding signals a, b or c on the respective modulator drive signallines from the output control device 110 of the digital portion 84. Thethree modulator drive signals a, b and c are TTL level switching signalswhich, when at an up level, turn on their respective phase modulators104a, 104b or 104c. The delays of the three signal paths of the phasemodulators 104a, 104b and 104c are 0, 120 and 60 degrees, respectively.The 60 degree or phase modulator 104c path is, for purposes of thepresent invention, the reference phase of the composite signal at theoutput of the phase modulator device 102. The other two paths, 0° and120 degrees, would then be ±60°, respectively, relative to the referencephase.

Referring now primarily to FIG. 4, the sequence of switching between thephase modulators 104a, 104b and 104c is such that only one of them is onat a time. The phase modulator 104a, corresponding to the 0 degree path,is on for 2.5 milliseconds (ms). Then, the phase modulator 104b,corresponding to the 120 degree path, is on for 2.5 ms, followed by thephase modulator 104c, corresponding to the 60 degree path, being on for5.0 ms. In the satellite modulation format, this sequence of 0, 120 and60 degrees of phase modulation upon the 400 MHz-26 kHz signalcorresponds to phase modulation changes of +60, -60 and 0 degrees,respectively, which is termed a "+ doublet". As shown, a "- doublet"corresponds to phase modulation changes of -60 degrees for 2.5 ms, +60degrees for 2.5 ms, followed by 0 degrees for 5.0 ms. Thus, a bitequivalent to a binary "one" corresponds to a "+ doublet" followed by a"- doublet". A bit equivalent to a binary "zero" corresponds to a "-doublet" followed by a "+ doublet", as shown in FIG. 4.

Referring again to FIG. 3, the sequencing of phase modulator drivesignals a, b, and c, is established by the test generator 106 incooperation with the output control device 110.

Mode B operation is the same as mode A except that an external 5 MHzsignal is brought into the satellite simulator section 80 from theescutcheon panel (not shown) via the buffer/mode select device 90. Whenthis signal is applied, three events take place. First, the buffer/modeselect device 90 operates to generate a mode change command signal onthe mode change command line (MCCL) to the crystal-controlled oscillatordevice 88 thereby cutting it off. Second, the buffer/mode select device90 selects the input 5 MHz signal and then amplifies and squares it tothe TTL level. This signal now becomes the reference signal to the inputof the phase comparator/loop filter 92. Third, the count down divider112, under control of, for example, the aforementioned mode changecommand line signal, an offset select switch on the escutcheon panel(not shown), generates a 26 KHz or 39 KHz signal for feeding the offsetmixer 116 of the interface portion 86. This operation is necessarybecause the output frequency of the radio frequency portion 82 in mode Boperation is eighty times the frequency of the 5 MHz reference signal.Consequently, the output of the radio frequency portion 82 will be near,or exactly at 400 MHz. However, the receiver under test, which forpurposes of the present invention is the AN/SRN-19(V)2, will not respondto an exact 400 MHz test signal. Thus, by passing the signal through theoffset mixer 116, in cooperation with the output from the count downdivider 112, a usable signal is generated either at 400 MHz-26 KHz or400 MHz-39 KHz, depending on the position of the offset select switch,aforementioned. In mode B operation, the mixing signal (26 KHz or 39KHz) is derived from a count down of the 100 MHz output of the VCO 96.This count down is partially accomplished by the frequency divider 94(divide by 20) in cooperation with the frequency divider 98 (divide by2). In mode B operation, the phase modulation of the approximately 400MHz signal is the same as in mode A. However, in mode B operation thefrequency stability is better than in mode A, and, accordingly, suitablefor measuring the doppler reconstruction circuitry (not shown) and thefrequency stability of the 5 MHz reference oscillator (not shown) of theassociated AN/SRN-19(V)2.

The primary purpose of the digital portion 84 of the satellite simulator80 of FIG. 3 is to generate the sequence of digital data (signals a, band c) for driving the phase modulator device 102. The digital data aresimilar to that from a system satellite in terms of having a repeatingmessage data pattern, as generated by the test message generator 106,and a two minute synchronization data pattern, as generated by the syncword generator 108. The test message generator 106 is configured togenerate a signal (message data) corresponding to a repeating sequenceof two binary "ones" followed by two binary "zeros". The test messagegenerator 106 continually outputs this repeating pattern via the outputcontrol device 110 as the drive signals a, b and c. The drive signal forthe test message generator 106 and the count down divider 112 is a 2.5MHz signal from the output of the frequency divider 98 of the RF portion82. As also controlled from the escutcheon panel (not shown), the syncword generator 108 is configured to generate a sync word consisting of25 binary bits, i.e, a "zero", 23 "ones" and another "zero" in thatorder. Since each binary bit, "one" or "zero" requires 20.0 ms as, shownin FIG. 4, a sync word requires 0.5 seconds. After a sync word iscompleted, the output control device 110 in cooperation with the testmessage generator 106 automatically recommences the repeating messagedata sequence from the test message generator 106, as previouslydescribed.

The interface portion 82 serves to interface the test signal, at threedifferent predetermined power levels, to the associated navigationalsatellite receiver under test via the output of the tri-level attenuator120 (direct connection), or via the other output of the RF switch 188(indirect connection) to a radiating antenna (not shown). Theafore-mentioned two units are controlled by the direct/indirect testcontrol device 114, which acts to switch between direct testing orindirect testing, of the associated navigational satellite receiver.

To those skilled in the art, many modifications and variations of thepresent invention are possible in light of the above teachings. It istherefore to be understood that the present invention can be practicedotherwise than as specifically described herein and still be within thespirit and scope of the appended claims.

What is claimed is:
 1. A digital card tester section of a test set fordetecting the reduced capabilities of an associated navigationalsatellite receiver, said digital card tester section being configured togenerate signals (signatures) for testing and isolating faults in apredetermined number of digital system cards of the associatednavigational satellite receiver according to a predetermined program,said digital tester card section comprising:a read-only memory (ROM)being configured to store the predetermined program which corresponds toat least the signatures of the predetermined numbers of digital systemcards under test; a random access memory (RAM) being configured topermit data, in the form of the signatures, and in the form ofresponses, from the predetermined number of digital cards under test tobe stored or retrieved at comparable intervals according topredetermined periodic signals; a system clock for generating thepredetermined periodic signals for proper synchronization of signatures,responsive signals, and timing signals; a microprocessor operativelyconnected to said ROM, to said RAM and to said system clock for decodingand executing the predetermined program stored in said ROM; connectionmeans for operatively connecting the predetermined number of digitalsystem cards under test to said microprocessor and said RAM;intialization means operatively connected to said microprocessor forinstituting initialization thereof, and of said ROM and said RAM; anddisplay means operatively connected to said microprocessor fordisplaying the output of the RAM for the predetermined number of digitalsystem cards, and for indicating the faults therein.
 2. The digital cardtester section of claim 1 wherein said connection means comprises:adigital card socket device configured to support and electricallyconnect the predetermined number of digital system cards when insertedtherein; and a bi-directional buffer operatively connected between saiddigital card socket device, said RAM and said microprocessor fortransferring data under the control of said microprocessor, to and fromsaid digital card socket device and to and from said RAM.
 3. The digitalcard tester section of claim 2 wherein said digital card socket deviceof said connection means includes a predetermined number of digital cardsockets corresponding to the predetermined number of digital systemcards, each socket being configured one-to-one for each digital systemboard.
 4. The digital card tester section of claim 3 wherein saidinitialization means comprises:a digital card select device operativelyconnected to said microprocessor and being configured to be set to adigital socket position corresponding to one of the predetermined numberof digital card sockets so as to generate a digital word in responsethereto; and a system reset switch operatively connected to saidmicroprocessor and being configured to generate an interrupt thereto,after the particular digital system card to be tested is inserted in theproper one of the predetermined number of digital card sockets, so as tocommence the initialization process.
 5. The digital card tester sectionof claim 4 wherein said display means comprises:a pass indicatoroperatively connected to said microprocessor for indicating a passedcondition for the one of the predetermined number of digital systemboards under test; a fail indicator operatively connected to saidmicroprocessor for indicating a failed condition for the one of thepredetermined number of digital system boards under test; and a displaydevice operatively connected to said pass indicator and to said failedindicator, via said microprocessor, for displaying information, in theform of a digital word, as to whether the one of the predeterminednumber of digital system boards under test passed or failed, and iffailed, what part thereof failed.
 6. The digital card tester section ofclaim 5 wherein said pass indicator comprises:a green light-emittingdiode (LED); and a lamp driver operatively connected between said greenLED and said microprocessor such that, under control of saidmicroprocessor, said green LED is illuminated if an error flag is notset in said RAM when the predetermined signature of the one of thepredetermined number of digital system boards under test is comparedwith the response therefrom.
 7. The digital card tester section of claim6 wherein said fail indicator comprises:a red light-emitting diode(LED); and another lamp driver operatively connected between said redLED and said microprocessor such that under control of saidmicroprocessor, said red LED is illuminated if an error flag is set insaid RAM corresponding to a discrepancy when the predetermined signatureof the one of the predetermined number of digital system boards undertest is compared with the output response therefrom.
 8. The digital cardtester section of claim 7 wherein the predetermined program stored insaid ROM includes a self-test routine.
 9. The digital card testersection of claim 8 wherein said ROM comprises a programmable read-onlymemory (PROM) for changing the signature data therein to correspond toother than the predetermined number of digital system cards, if desired.